Dialer with internal option select circuit programmed with externally hardwired address

ABSTRACT

An option select circuit for a dialer includes an internal address generator (20) for generating an address pattern, which, in a set up mode, is output from a multiplexer (14) to I/O pins (10). The pins (10) are selectively hardwired through an interface circuit (24) back to address input pins (50) and (52) for input to a decorder (28). The decoder (28) decodes the selected address for input to a PLA (30). This allows selection of various functions in a function generator (12) for operation in the normal dialer mode. The interface circuit (24) comprises hardwire connections (54) and (56).

.Iadd.CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.08/679,314, filed Jul. 12, 1996, now abandoned, which is a continuationof U.S. patent application Ser. No. 08/539,423, filed Oct. 5, 1995, nowabandoned, which application is a continuation of U.S. patentapplication Ser. No. 08/373,887, filed Jan. 17, 1995, now abandoned,which application is a continuation of U.S. patent application Ser. No.07/824,851, filed Jan. 23, 1992, now abandoned, which application is aReissue of U.S. patent application Ser. No. 07/264,902, filed Oct. 31,1988, which issued as U.S. Pat. No. 4,896,060, which patent has beensurrendered. .Iaddend.

TECHNICAL FIELD OF THE INVENTION

The present invention pertains in general to address circuits foraddressing an internal PLA and, more particularly, to a multiplexingcircuit for internally generating an address and externally connectingthe address to an address input for the PLA.

BACKGROUND OF THE INVENTION

Automatic telephone dialer systems provide a specified output on thetelephone line in response to depressing telephone keys. However, theoutput provided by the telephone dialer is a function of a country inwhich that dialer is used. This output varies for a number of differentcountries. For example, there are sixteen different dialer formats inthe world. This, therefore requires a dialer that is to operate in allcountries to be of sufficient versatility to accommodate the differentdialing formats. At present, this typically requires a mask-change on aparticular chip to provide a dedicated chip for the associated country.This is undesirable from a production stand point and it would be muchmore desirable to provide a universal chip which could be programmedexternally.

When designing with universal logic, some type of programmable logicsuch as a PLA is normally utilized. The PLA can be programmed to providea fixed logic function or it can be programmed for multiple functionsthat are addressable. In the fixed function logic array, the programmingis done with a mask change such that a given dialer chip is useful foronly a single country after fabrication thereof. An addressable array,on the other hand, provides the ability to have multiple functions on agiven chip after fabrication thereof. The disadvantage to theaddressable array, however, is the requirement for additional pins toaccept the address input and the requirement for an address generator.In view of these disadvantages, there exists a need to select from anumber of different functional options without significantly increasingthe number of pins.

SUMMARY OF THE INVENTION

The present invention disclosed and claimed herein comprises aprogrammable control circuit. The control circuit includes a pluralityof input/output pins which are interfaced with a function generator andan internal address generator. The address generator is selected by amultiplexer during a set-up mode for interface with the input/outputpins and is operable to generate a separate and predetermined serialaddress for each of the I/O pins. A plurality of address input pins areprovided having a number less than the plurality of I/O pins, and areoperable to be interfaced with the I/O pins. The address input pins areselectively connected through interface circuitry to a select one of theI/O pins depending upon the desired address. A decoder is provided fordecoding the received address on the address input pin and latching thisdecoded address into the register during the set-up operation. Thisaddress is then input to an addressable control signal generator foroutput of a separate and predetermined function for each decodableaddress. These control signals are then input to the function generatorto provide control inputs therefore. Control circuitry is provided foroperating the control circuit in the set-up mode in response toreceiving an external set-up signal.

In another embodiment of the present invention, each of thepredetermined addresses is a binary address wherein the decoder circuitis operable to receive the serial address and convert it to a paralleladdress. The control signal generator is a programmable logic arrayhaving an address input and a separate and predetermined control outputfor each decodable address.

In yet another aspect of the present invention, the address generator,function generator, multiplexer, decoder, control signal generator andcontrol circuitry are all enclosed in a single package with the I/O pinsand the address input pins providing an interface with the exterior ofthe package. The interface circuitry is contained exterior to thepackage and comprises a hardwire connection between each of the addressinput pins and a select one of the I/O pins.

In yet a further aspect of the present invention, the control circuitryis operable to generate an internal set-up signal in response toreceiving an external set-up signal. The internal set-up signal isgenerated for a predetermined duration of time during which the addressgenerator is interfaced with the I/O pins and the decode circuit isoperable to decode the received address. At the end of this duration oftime, the decoded address is latched onto the address input of thecontrol signal generator, and then the function generator interfacedwith the I/O pins.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and theadvantages thereof, reference is now made to the following descriptiontaken in conjunction with the accompanying.[.D.]..Iadd.d.Iaddend.rawings in which:

FIG. 1 illustrates a basic block diagram of the present invention;.

FIG. 2 illustrates a more detailed block diagram of the dialer;

FIG. 3 illustrates a detailed diagram of the scan logic and multiplexingcircuitry;

FIG. 4 illustrates a logic diagram of the phase generator;

FIG. 5 illustrates a logic diagram of the multiplexing circuit;

FIG. 6 illustrates a logic diagram of the select decoder and PLA; and

FIG. 7 illustrates a logic diagram of the counter circuitry forgenerating the timing control.

It will be appreciated that for purposes of clarity and where deemedappropriate, reference numerals have been repeated in the figures toindicate corresponding features in order to more clearly show importantfeatures of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to FIG. 1, there is illustrated a block diagram of thedialer of the present invention. The dialer interfaces with a switchmatrix (not shown) through a plurality of input/output (I/O) pins 10.The I/O pins 10 are then scanned in accordance with the predeterminedscan-logic routine to determine which of the switches in the matrix hasbeen depressed. This is a conventional operation utilizing conventionalcircuitry. In normal operation, a function generator 12 is providedwhich interfaces with the I/O pins 10 through a multiplexer 14. Thefunction generator 12 has the output thereof connected to one input ofthe multiplexer 14 and the output of the multiplexer 14 is thenconnected to the I/O pins 10. The function generator 12 is operable tosense which of the keys in the switch matrix has been depressed and thengenerate an output dialing pattern for output from the dialer (notshown). In departing from the conventional function generator, thefunction generator 12 of the present invention is operable to beprogrammed, as will be described in more detail hereinbelow, to providethe dialing function for a particular country in response to selectedcontrol input signals.

When the book switch is initially closed (i.e., off-hook condition), ahook switch signal HKS is generated. This initial action is detected bya detect/counter circuit 16 to output a control signal on a line 18 fora predetermined duration of time. This control signal is operable toinitiate a programming sequence to determine a particular countrydialing format each time the HKS signal is generated; that is, each timethe receiver is removed from the hook switch, the dialer of the presentinvention is configured for a particular country in accordance with apredetermined dialing format, as will be described hereinbelow.

Once placed in the reconfiguration mode, an address generator 20 isselected as the other input of the multiplexer 14 for connection to theI/O pins 10 and the function generator 12 deselected. Therefore, the I/Opins 10 are now utilized to output addresses thereon. These addressesare selectively connected through lines 22 and interface circuit 24 toprovide on the output thereof a predetermined orientation of theaddresses. As will be described in detail hereinbelow, the interfacecircuit 24 is operable to select the combination of addresses output onthe I/O lines 10 for output on a bus 26, which hardwire interface isdetermined by the installer. The bus 26 provides select input signals toa decoder 28 in the preferred embodiment. Thus the interface circuit 24in the preferred embodiment comprises a hardwire interface between theI/O pins 10 and the bus 26, which hardwire interface is determined bythe installer. The interface circuit 24 is operable to provide theparticular configuration for a given country. The interface circuit 24in the preferred embodiment is external to the chip.

The decoder 28 is operable to decode the addresses on the select bus 26for output to a programmable logic array (PLA) 30. The PLA 30 isoperable to receive the address and latch the address therein and then,in accordance with a predetermined addressable logic function, outputcontrol signals on a plurality of control lines 32. Each of the controllines 32 is operable to determine the function of the functiongenerator, the control lines 32 being input to the function generator12. The PLA 30 is therefore configured during the initial predeterminedtime, in response to a signal from the detect/counter circuit 16, andthen the logic state thereof latched for use by the function generator12. As described above, this address generation and decoding thereofoccurs each time the hook switch signal HKS is generated. Once set up,after the programming sequence, the dialer then enters into aconventional mode and generates the particular functions for the desiredcountry, as determined by the interface circuit 24. In order toreconfigure the dialer for a different country, it is only necessary tochange the configuration in the interface circuit 24.

Referring now to FIG. 2, there is illustrated a more detailed blockdiagram of the preferred embodiment of the dialer of the presentinvention. The dialer is contained within a chip boundary 34 and thefunctional portion of the dialer operating in the normal operating modegenerally comprises a scan logic block 36. The scan logic block 36generally corresponds to the function generator 12 and multiplexer 14 ofFIG. 1. The scan logic block 36 interfaces with four I/O terminals 38comprising the R-terminals of an external matrix and also interfaceswith four I/O terminals 40 associated with the C-terminals of anexternal switch matrix. The address generator 20 interfaces through abus 42 with the scan logic block 36. The address generator 20 isoperable to interface with a phase generator 44 and also with a counter46. The counter 46 is similar in function to the detect/counter circuit16 of FIG. 1.

The phase generator 44 is operable to generate four separate clocksignals separated in phase by 90°. The four clocks are then utilized bythe address generator to generate serial addresses, as will be describedhereinbelow.

A select/decode circuit 48 is provided which is similar in function tothe decoder 28. The select/decode circuit 48 interfaces with two I/Oterminals, an A-terminal 50 and a B-terminal 52. The A and B I/Oterminals 50 and 52 are a portion of the select bus 26 of FIG. 1. Theoutput of the select/decode circuit 48 is input to the PLA 30 togenerate the control signals for output on the control lines 32. Thecontrol lines 32, as described above, are then input to the scan logicblock 36 to determine the particular function thereof.

In order to generate the address for the PLA 30, it is necessary tofirst output a separate and predetermined address on each of theR-terminals 38 and the C-terminals 40 with the address generator 20.During the initial operation sequence of the dialer that is initiated bygoing off-hook, as defined by the counter 46, an internal multiplexer tothe scan logic block 36 selects the output of the address generator foroutput on the R-terminals 38 and the C-terminals 40. These arepredetermined addresses, and in the preferred embodiment, comprise aseries of logic "1"s and logic "0"s.

To determine or select the address, it is only necessary to connect theA-terminal 50 to one of the R-terminals 38 or the C-terminals 40 andalso connect to the B-terminal 52 to one of the R-terminals 38 or theC-terminals 40. In the example illustrated in FIG. 2, a dotted linerepresents a hardwire connection between the A-terminal 50 and thesecond terminal in the R-terminals 38 through hardwire line 54. Inaddition, a hardwire line 56, represented by a dotted line, is connectedbetween the B-terminal 52 and the fourth terminal in the C-terminals 40.This provides a unique address which is decoded by the select/decodecircuit 48 for generating the address for the PLA 30. It is thereforeonly necessary for an operator to install the dialer circuit 34 withpredetermined "jumpers" between the R-terminals 38 and the C-terminals40 and one of the A-terminals 50 and B-terminals 52 to provide theappropriate address. Therefore, the dialer chip 34 is a universal dialerwhich can be externally programmed wherein the program for all sixteencountries is contained internal to the chip and selection of thatfunction requires only two additional pins or terminals to the circuit.As will be described hereinbelow, the two additional terminals allowselection of one of sixteen countries and, for each country, one of fourselect functions for that particular country. This therefore providesthe ability to select up to 64 options with only the addition of twoterminals or pins on the chip 34.

The address generator 20 is operable to select the various phases of thephase generator 44 for combination thereof and output of a separateserial four-bit word on each of the R-terminals 38 and C-terminals 40.The particular sequence of logic bits is illustrated in Table 1 with thefour R-terminals 48 labelled R1-R4 and the four C-terminals 40 labelledC1-C4.

                  TABLE I                                                         ______________________________________                                               Terminal                                                                             Bit Value                                                       ______________________________________                                               R1     0111                                                                   R2     1011                                                                   R3     1101                                                                   R4     1110                                                                   C1     1000                                                                   C2     0100                                                                   C3     0010                                                                   C4     0001                                                            ______________________________________                                    

Only the three least significant bits are utilized wherein R1 has thethree-bit value "111" and the C1 terminal has the bit value "000" outputthereon during the initial setup. It can be seen therefore, that thereare eight possible combinations if only one of the A-terminals 50 orB-terminals 52 were utilized. However, with both the A-terminal 50 andthe B-terminal 52, it is possible to select the bits in such a manner asto make up a six-bit word since all possible combinations of six arepresent in the first three bits of the R-terminals 38 and theC-terminals 40.

By way of example, the R2 terminal 38 is selected for connection to theA-terminal 50 and the C4 terminal is selected for connection to theB-terminal 52. This would result in a selection of the three-bit value"011" for input to the A-terminal 50 and the selection of the three-bitvalue "001" for input to the B-terminal 52. This would result in adigital word with a value of "001011". This would constitute the addressfor the PLA 30 if all six bits were utilized.

In the preferred embodiment, as will be described in more detailhereinbelow, the sixteen countries are selected by selecting one of theeight values from the R-terminal 38 or the C-terminals 40 for input tothe A-terminal 50 and decoding the three-bit value to determine thatparticular value while determining whether one of the C-terminals 40 orone of the R-terminals 38 were selected for input to the B-terminal 52.This effectively provides a four-bit word to provide sixteencombinations for the sixteen countries. Thereafter, an additionaltwo-bits are decoded to provide additional information for each of thecountries.

Referring now to FIG. 3, there is illustrated a more detailed diagram ofthe multiplexing circuit 14 that is internal to the scan logic block 36.The scan logic block 36 is interfaced with a switch matrix 58 whichillustrates one connection of a horizontal line to one of theR-terminals 38 and one connection of a vertical line to one of theC-terminals 40. Each of the terminals is connected to a node 60 which isinput to a flip flop 62. The flip flops 62 operate in accordance withthe scan logic and are not utilized in the set-up operation. Each of thenodes 60 is connected through a P-channel load transistor 64 to apositive supply and through the source-to-drain path 66 of an N-channeltransistor to ground. The gate of the N-channel transistor is operableto modulate the node 60 to provide a pin driver. The gates of each ofthe transistors 66 is connected through a multiplexing circuit 68 toeither the function generator 12 or the address generator 20. In thenormal mode of operation, the function generator 12 is operable tooperate in a scan mode to determine which of the keys in the matrix 58are depressed and then select the proper output dialing functions forthe already designated country. The connections between the key matrixand the function generator 12 are not shown in FIG. 3. However, in theset-up mode, the address generator 20 is selected for outputting aserial address pattern on the associated I/O terminals 38 or 40. The pindriver therefore operates as an inverter during the set-up operation,when the keys are not depressed and the matrix 58 does not take any partin the set-up operation. Although not illustrated in FIG. 3, duringset-up, a select one of the I/O terminals 38 or 40 is connected to theA-terminal 50 and the B-terminal 52.

Referring now to FIG. 4, there is illustrated a logic diagram of thephase generator 44. The phase generator 44 is operable to receive aclock CLK4 that is four times the system clock rate. The inverted andnon-inverted form of a clock CLK4 is provided with an inverter 72 and isinput to series-connected D-type flip flops 74 and 78 with the Q-outputof flip flop 74 connected to the input of flip flop 78. The Q-bar outputof flip flop 78 is connected to the D-input of flip flop 74. The setinput of both flip flops 74 and 78 are connected to a signal ACCESS-bar.The flip flop 74 outputs a clock signal QL and QL-bar and the flip flop78 outputs clock signals QM and QM-bar. The QM output is connected toone input of a four-input AND gate 80 and also to one input of athree-input AND gate 82. The QM-bar output is connected to one input ofa three-input AND gate 84 and also to one input of a three-input ANDgate 86. The four-input AND gate 80 has one input thereof connected tothe QL output of flip flop 74, one input thereof connected to the CLK4clock signal and one input thereof connected to the output of aninverter 88 which has the input thereof connected to the ACCESS-barsignal. The AND gate 82 has the other two inputs connected to the clockCLK4 and the QL-bar clock signal, respectively. The other two inputs ofthe AND gate 84 are connected to the CLK4 clock signal and the QL-barclock signal. The AND gate 86 has the other two inputs thereof connectedto the .[.QM-bar.]. .Iadd.CLK4 .Iaddend.clock signal and the QL clocksignal.

The AND gate 80 has the output thereof connected to one input of a NORgate 90, the other input thereof connected to ground. The AND gate 82has the output thereof connected to one input of a NOR gate 92, theother input thereof connected to ground. The AND gate 84 has the outputthereof connected to one input of a NOR gate 94, the other input thereofconnected to ground. The AND gate 86 has the output thereof connected toone input of a NOR gate 96, the other input thereof connected to ground.The NOR gates 90-96 provide the phase generator outputs.[.01-bar-04-bar.]. .Iadd.D1-bar-D4-bar.Iaddend.. Each of the NOR gates90-96 are gated to a high impedance state by a P-channel transistor 98having the source-to-drain path thereof connected between V_(CC) and thegate input to the NOR gates with the gate thereof connected to ground.The phases provided are therefore equal to a pulse occurring at a rateequal to the master clock but with the leading clock edges offset by 90°from each other. The pulse width of each of the clocks.[.01-bar-04-bar.]. .Iadd.D1-bar-D4-bar .Iaddend.is equal to one fourthof the pulse width of the master clock.

Referring now to FIG. 5, there is illustrated a logic diagram of themultiplexing circuit 68 shown in FIG. 3 and a portion of the addressgenerator 20. The multiplexer 68 is comprised of a plurality ofmultiplexing circuits, each associated with one of eight outputs, fouroutputs associated with the R-I/O terminals 38 and four of the outputsassociated with the C-I/O terminals 40. Each of these outputs drives thegate of the N-channel driver transistor 66 in the output terminaldriving circuit, as described above, with reference to FIG. 3. There arefour inputs Q1-Q4 which are associated with the scan logic function inthe function generator 12, and these four inputs are provided in thetrue and the complement form, the complement form being generated by abank of four inverters 100. In addition, phase inputs are provided fromthe phase generator 44. These phase inputs are PHI2-bar-PHI4-bar and thesignal SS which indicates the condition of the hook switch signal HKS.Each of the signals SS and PHI2-bar-PHI4-bar are provided in the trueand the complement form, the complement form being provided by a bank ofinverters 102.

The outputs are divided into two groups, a first group labelled K91-K94and a second group labelled K95-K98. The outputs K92 and K93 in thefirst group are associated with multiplexers comprised of a two-inputNOR gate 104 having one input thereof connected to the output of atwo-input AND gate 106 and the other input thereof connected to theoutput of a two-input AND gate 108. The output K94 in the first groupand the outputs K95-K97 in the second group are each associated with amultiplexer having a two-input NOR gate 110 on the output thereof. Oneinput of the NOR gate 110 is connected to the output of a two-input ANDgate 112 and the other input thereof is connected to the output of athree-input AND gate 114. The output K91 in the first group is connectedthrough an inverter 116 to the SS signal. The output K98 in the secondgroup is connected to the output of a three-input NAND gate 118, oneinput of which is connected to the Q4 input, one input of which isconnected to the Q3-bar output and the other input of which is connectedto the SS-bar signal.

The output K92 has the inputs of the AND gates 106 and 108 connectedsuch that one input of AND gate 106 is connected to the PHI4-bar signal,and the other input thereof connected to the SS signal. AND gate 108 hasone input thereof connected to the Q2 output and the other input thereofconnected to the SS-bar signal. The K93 output has the AND gates 106 and108 thereof connected such that one input of AND gate 106 is connectedto the PHI3-bar signal and the other input thereof is connected to theSS signal. The associated AND gate .[.10B.]. .Iadd.108 .Iaddend.has oneinput thereof connected to the Q1 output and the other input thereofconnected to the SS-bar input. The multiplexer associated with the K94output has one input of the two input NAND gate 112 connected to thePHI2-bar signal and the other input thereof connected to the SS input.The associated three-input AND gate 114 has one input thereof connectedto the Q2-bar input, one input thereof connected to the Q1-bar input andthe other input thereof connected to the SS-bar input.

In the second group of outputs, the multiplexer associated with the K95output has the two inputs of associated AND gate 112 connected to thePHI2.[.-bar.]. input and the SS input, respectively, and the three-inputAND gate 114 has the inputs thereof connected to the Q4-bar input, theQ3-bar input and the SS-bar input. In a similar manner, the multiplexerassociated with the K96 output has the two inputs of associated AND gate112 connected to the PHI3 input and the other input thereof connected tothe SS inputs, respectively. The associated three-input AND gate 114 hasone input thereof connected to the Q4-bar input, one input connected tothe Q3 input and the other input thereof connected to the SS-bar input.The multiplexer associated with the K97 output has the two inputs ofassociated AND gate 112 connected to the PHI4 and the SS input,respectively. The associated three input AND gate 114 to has one inputthereof connected to the Q3 input, one input thereof connected to the Q4input and one input thereof connected to the SS-bar input.

In operation, the SS input signal is operable to select for the set-upmode when it is high and to deselect when it is low. Therefore, when theSS input signal is high, the K91 output is low and the K98 output ishigh and remains high. The remaining outputs are defined as a functionof the phase inputs PHI2-bar-PHI4-bar. As described above, this occursonly during the set-up operation which is defined by the duration duringwhich the SS.[.-bar.]. input signal is high.

Referring now to FIG. 6, there is illustrated a logic block diagram ofthe select/decode circuit 48 and PLA 30 of FIG. 2. Included in FIG. 2are two inputs, an SELB input and an SELA input, the SELB input beinginput on the B terminal 52 and the SELA input being input on the Aterminal 50. The SELB input is connected to one input of a two-input ORgate 120, the output of which is connected to one input of a two-inputNAND gate 122. The other input of the OR gate 120 is connected throughan inverter to a test circuit (not shown) which is always low during theset-up operation. The other input of NAND gate 122 is connected to theoutput of a four-input NAND gate 124. NAND gate 124 has four inputsconnected to various clock signals, one input connected to a CLK input,one input connected to a CLK8 signal and one input connected to a clocksignal ENSS, which is generated during the set-up operation.

During the set-up operation, the test signal is low such that the outputof OR gate 120 is always high, the SELB signal in line 52 not affectingthe output of OR gate 122. This results in NAND gate 122 having anoutput that is a function of the clock signals on the output of NANDgate 124. Since the other input signals are high during set-up, theoutput of NAND gate 122 is the CLK4 signal. The clock signal output byNAND gate 122 is input to the clock input of another threeseries-connected D-type flip flops 126, 128 and 130 and also to theclock input of three series-connected D-type flip flops 132, 134 and136. The D-type flip flops 126-130 are configured such that the Q outputof flip flop 126 is connected to the D-input of flip flop 128 and theQ-output of flip flop 128 is connected to the D-input of flip flop 130.The SELA signal on line 50 is connected to the D-input of flip flop 126.

In a similar manner, the flip flop 132 has the Q-output thereofconnected to the D-input of flip flop 134 and the Q-output of flip flop134 is connected to the D-input of flip flop 136. The D-input of flipflop 132 is connected to the output of a NAND gate 138. NAND gate 138has one input thereof connected to the output of an OR gate 140 and theother input thereof connected to the input of an OR gate 142. OR gate140 has one input thereof connected through an inverter 144 to the testsignal and the other input thereof connected to the Q-bar output of flipflop 130. The OR gate 142 has one input thereof connected to the testinput and the other input thereof connected to the SELB input on line52. When the test signal is low and prior to the Q-bar output of flipflop 130 going high, the output of OR gate 140 is always high and theoutput of OR gate 142 is determined by the logic state of SELB on line52.

The flip flops 126-130 are operable to store the three-bit value of theserial address input on the SELA terminal 50. In a similar manner, thethree flip flops 132-136 are operable to store the serial address valueinput on the SELB terminal 52. The Q and Q-bar outputs of the flip flops126-130 are input to an option select PLA to provide a one of eightselection. In a similar manner, the three flip flops 132-136 have theQ-bar outputs thereof input to a decode circuit 148 which has the trueand complement form thereof input to the option select PLA 146. Thedecode circuit 148 essentially decodes whether the three-bit value inthe flip flops 132-136 correspond to one of the four values on eitherthe R-terminals 38 or the C-terminals 40. The decode circuit 148 iscomprised of three two-input OR gates, the outputs thereof connected tothe inputs of a three-input NAND gate. The output of the three inputNAND gate providing the output of the decode circuit 148. The first andsecond OR gate in the decode circuit 148 have one input thereofconnected commonly to the Q-bar output of flip flop 132. The first andthird OR gates have one input thereof commonly connected together to theQ-bar output of flip flop 134. The second and third OR gates have oneoutput thereof connected in common to the Q-bar output of flip flop 136.Therefore, whenever there are at least two zeros stored in flip flops132-136, the output of the decode circuit 148 will be a logic low. Thiswill indicate that the received address is one of the address valuesgenerated by the C-terminals 40 and, whenever there are at least twologic "1"s stored in flip flops 132-136, the output decode circuit 148will be a logic high, indicating one of the address values output by theR-terminal 38. Therefore, decode circuit 148 detects whether the PLAaddress input is connected to the R-terminals 38 or the C-terminals 40,providing an additional bit of information. In combination with the SELAaddress, this provides a four-bit address input to the option select PLA146.

The option select PLA 146 is operable to provide sixteen outputs on bus32 indicating sixteen different country codes or sixteen selections.This information is then output to the function generator 12 todetermine the various parameters for the output dialing format for thatparticular country.

In operation, generation of the HKS signal upon removing the receiverfrom the hook results in a reset signal being sent to each of the sixflip flops 126-138 to set the Q-output thereof low and the Q-bar outputthereof high. This is facilitated through the HKS input being connectedto each of the reset inputs on the flip flops 126-136 through a line150. In addition, the ENSS signal is generated which is an enable signalfor the set-up mode. As described above, a counter 46 is initiated whichis operable for four clock cycles to generate the addresses from theaddress generator 20 and output these on the R-terminal 38 and theC-terminal 40 through the hardwired connections 54 and 56 to the SELBterminal 52 and the SELA terminal 50. This occurs until the counter 46has timed-out, at which time the ENSS signal goes low and the data islatched as an address to the option-select PLA 146. This operationoccurs each time the receiver is lifted such that any errors or glitchesthat occur in the address stored in the flip flops 126-138 will becorrected for. This is essentially an automatic reset operation.

In order to generate more address bits, the data stored in the flipflops 132-136 is further decoded by two exclusive OR gates 152 and 154.Exclusive OR gate 152 has one input thereof connected to the Q-output offlip flop 134 and the other input thereof connected to the Q-output offlip flop 136. In a similar manner, exclusive OR gate 154 has one inputthereof connected to the Q-output of flip flop 132 and the other inputthereof connected to the Q-output of flip flop 136. Exclusive OR gates152 and 154 provide an additional two-bits of address information whichis utilized for separate functions for the selected country in theoption select PLA 146. Therefore, it can be seen that the additional twoterminals 50 and 52 have allowed a total addressing capability ofsixty-four options, although all sixty-four of these options were notutilized.

Referring now to FIG. 7, there is illustrated a block diagram of thecounter 46 that is comprised of binary counter 160 which has a pluralityof binary outputs for generating a binary count value. The counter iscontrolled by the master clock and also a reset signal. The reset signalis generated initially upon receipt of the HKS signal when the initialset-up operation is begun. This reset signal resets the counter to avalue of zero on all outputs thereof and also resets the Q-bar output ofa latch 162 to a logic "1". The latch 162 has the clock input thereofconnected to the master clock and also has the data input thereofconnected through a two-input AND gate 164 to the first two bits ofcounter 160. Therefore, when the counter 160 has counted four values, aone is present on both inputs of the AND gate 164 resulting in a one onthe data input of latch 162. When this logic one is clocked through tothe Q-bar output thereof as a logic "0", it will remain latched thereuntil reset. The latch 162 is therefore operable to latch the SS signallow after four counts. Therefore, the latch 162 is operable inconjunction with the counter 160 to allow the set-up operation to beinitiated during the first four counts of the counter 160. This is inresponse to a reset operation which occurs whenever the hook switch isclosed.

In summary, there has been provided an address scheme for a dialer. Theaddress scheme utilizes an internal multiplexing circuit formultiplexing internal pins to output an internally generated address fora hardwire connection to other pins on the circuit. The predeterminedaddress patterns that are output during a program mode are selectivelyhardwired to the decode pins with the decode operation recovering theinternally generated address for input to a PLA. The output of the PLAprovides control lines for determining the final function of the dialer.Therefore, the internal address generator allows selection between aplurality of functions with only a minimum number of additional pinsrequired for this feature.

Although the preferred embodiment has been described in detail, itshould be understood that various changes, substitutions and alterationscan be made therein without departing from the spirit and scope of theinvention as defined by the appended claims.

What is claimed is:
 1. A programmable control circuit, comprising:aplurality of input/output pins; an address generator for generating aseparate and predetermined serial address for each of said input/outputpins; a function generator for interfacing with said input/output pinsto perform a predetermined function; a multiplexer circuit for selectingsaid function generator when in a normal mode of operation or saidaddress generator when in a set-up mode of operation to interface withsaid input/output pins; a plurality of address input pins having anumber less than that of said plurality of input/output pins; interfacemeans for interfacing select ones of said input/output pins with selectones of said address input pins; decode means for decoding and latchingsaid addresses received on said address input pins during said set-upoperation; an addressable control signal generator for outputting aseparate and predetermined control signal for each decodable address,said predetermined control signals utilized by said function generator;and control means for generating a set-up signal to control saidmultiplexer to select said address generator and to control said decodemeans for decoding and latching said received addresses on said inputaddress pins.
 2. The control circuit of claim 1 wherein said functiongenerator performs a predetermined number of functions, each functionselected by one of said control signals output by addressable controlsignal generator.
 3. The control circuit of claim 1 wherein said addressgenerator, function generator, multiplexer, decode means, addressablecontrol generator and control means are contained with the boundaries ofa package and said input/output pins and address input pins interfacebetween the interior of said package and the exterior thereof, and saidinterface means is on the exterior thereof.
 4. The control circuit ofclaim 1 wherein said interface means comprises a plurality of hardwireinterconnections selectively connected between select ones of saidaddress input pins and select ones of said input/output pins.
 5. Thecontrol circuit of claim 4 wherein each of said address input pins isconnected to a select one of said input/output pins.
 6. The controlcircuit of claim 1 wherein said decode means comprises means forreceiving the serial address and decoding said serial address to outputa parallel address for input to said control signal generator.
 7. Thecontrol circuit of claim 1 wherein said control signal generatorcomprises a programmable logic array having an address input and acontrol signal output, each control signal output activated in responseto an associated address being input to the address input thereof. 8.The control circuit of claim 1 wherein said control means comprises:acounter for providing a predetermined count and initiated upon receivingan external set-up signal; and means for generating an internal set-upsignal during the operation of said counter, said internal set-up signalutilized to control said multiplexer, said address generator and saiddecode means during the set-up operation and inhibit the operation ofsaid function generator during this operation, said counter meansinitiating said internal set-up operation upon the occurrence of saidexternal set-up signal.
 9. The control circuit of claim 1 wherein saidinput/output pins are divided into at least two groups and said addressinput pins comprise at least two address input pins, said predeterminedaddresses being binary addresses, said decode means comprises aserial-to-parallel converter for converting the received binary addresson a first one of said address input pins to provide a parallel binaryaddress and means for determining which of said first and second groupsof said input/output pins was connected to said second of said addressinput pins to provide an additional binary bit of address informationfor input to said control signal generator.
 10. A method for generatingcontrol signals with a minimum number of pins on a given package,comprising:generating an internal function for operation in a normaloperation mode to interface through a plurality of input/output pins toan exterior of the given package; generating a separate andpredetermined serial address for each of the input/output pins during aset-up operation; selectively interfacing each generated serial addresswith the input/output pins during the set-up operation and the generatedinternal function with the input/output pins during the normaloperation; externally connecting select ones of the input/output pins toaddress input pins, the address input pins having a number less than theplurality of input/output pins; decoding and latching a received addresson the address input pins during the set-up operation; generating aseparate and predetermined control signal for each of said predeterminedserial address received, the control signals then utilized to controlthe function generation; and controlling with a control circuit to setan operate mode of either the set-up operation mode or the normaloperation mode.
 11. The method of claim 10 wherein the step ofgenerating an internal function comprises generating one of a pluralityof functions, each of the functions associated with each of the controlsignals and the one of the plurality of functions generated is generatedin response to generation of the control signal.
 12. The method of claim10 wherein the step of interfacing comprises hardwiring a select one ofthe input/output pins to a select one of the address input pins.
 13. Themethod of claim 12 wherein the step of hardwiring comprises hardwiringeach of the address input pins to a select one of the input/output pins.14. The method of claim 10 wherein the predetermined addresses arebinary addresses and the step of decoding comprises converting at leasta portion of the received address from a serial address to a paralleladdress.
 15. The method of claim 10 wherein the step of controllingcomprises:initiating the control set-up operation in response toreceiving the external set-up signal; and terminating the set-upoperation after a predetermined duration of time such that the set-upoperation is initiated each time the external set-up signal is received..Iadd.
 16. A programmable dialer control circuit having a programmingmode of operation and a normal mode of operation, and a plurality ofpins, wherein said control circuit is programmed by the presence orabsence of hardwired connections on said plurality of pins, and saidplurality of pins having other hardwired connections which conveyinformation to the control circuit during said normal mode of operation..Iaddend..Iadd.17. The programmable dialer control circuit set forth inclaim 16 wherein the operation of said control circuit during saidnormal mode of operation is determined, at least in part, during saidprogramming mode of operation. .Iaddend..Iadd.18. The programmabledialer control circuit set forth in claim 16 wherein said hardwiredconnections used to program the Programmable control circuit are alsoconnected to at least one additional input pin of the programmablecontrol circuit. .Iaddend..Iadd.19. The programmable dialer controlcircuit set forth in claim 16 wherein said program mode of operation isof a predetermined duration and initiated upon receipt of an externalsignal. .Iaddend..Iadd.20. The programmable dialer control circuit setforth in claim 16 wherein said other hardwired connections areinput/output pins. .Iaddend..Iadd.21. The programmable control circuitset forth in claim 20 wherein during said programming mode an address isgenerated in said dialer and placed on said plurality of pins and passedthrough said hardwired connections and received at another of saidplurality of pins. .Iaddend..Iadd.22. A method for generating controlsignals in a dialer control circuit comprising the steps of:a) placingsaid control circuit into a programming mode of a predetermined durationupon receipt of an external signal; b) Programming said control circuit,said programming being determined by external hardwired connections to aplurality of pins at the exterior of a chip containing said controlcircuit; and c) generating an internal function for operation in normalmode to thereby provide control signals, said internal function beingdependent on the programming of said control circuit, and said internalfunction also being dependant on the information conveyed on otherhardwired connections to said plurality of pins. .Iaddend..Iadd.23. Themethod for generating control signals in a dialer control circuit as setforth in claim 22 wherein said programming is determined by hardwiredconnections from at least one of said plurality of pins to at least oneother input pin of said chip, and further including the step ofgenerating and coupling a serial address out of said at least one ofsaid plurality of pins and into said at least one other input pin duringthe step of programming said control circuit. .Iaddend..Iadd.24. Adialer with an internal option select circuit programmed with at leastone external hardwired connection. .Iaddend..Iadd.25. The dialer setforth in claim 24 wherein said internal option select circuit selectsdialing parameters of the dialer such that, depending on the programmingof said internal option select circuit, dialing parameters of one of aplurality of countries can be selected. .Iaddend..Iadd.26. The dialerset forth in claim 24 wherein said at least one external hardwiredconnection is connected to at least one input pin of the dialer..Iaddend..Iadd.27. The dialer set forth in claim 26 wherein said atleast one external hardwired connection is connected to one input pin ofthe dialer. .Iaddend..Iadd.28. The dialer set forth in claim 26 whereinsaid at least one external hardwired connection is also connected to anadditional input pin of the dialer. .Iaddend..Iadd.29. The dialer setforth in claim 28 wherein said internal option select circuit isprogrammed during a set-up mode of the dialer, and during said set-upmode, a serial address is generated in the dialer and placed on said atleast one input pin of the dialer, said serial address also being passedthrough said at least one external hardwired connection and received atsaid additional input pin of the dialer. .Iaddend..Iadd.30. The dialerset forth in claim 24 wherein said internal option select circuit isprogrammed during a set-up mode of the dialer. .Iaddend..Iadd.31. Adialer having a normal mode of operation and a program mode ofoperation, said program mode of operation being of a predeterminedduration and initiated upon receipt of an external set-up signal..Iaddend..Iadd.32. The dialer set forth in claim 31 wherein saidexternal set-up signal is a hook switch signal. .Iaddend..Iadd.33. Thedialer set forth in claim 31 wherein during said program mode ofoperation the dialer becomes configured for a particular country suchthat during said normal mode of operation, and upon receipt of anexternal signal, the dialer provides a predetermined dialing format forsaid particular country. .Iaddend..Iadd.34. The dialer set forth inclaim 31 wherein the dialer is embodied on a chip, and during saidprogram mode of operation the dialer determines, by hardwiredconnections to the dialer which are external to the chip, a set offunctions which the dialer will perform during said normal mode ofoperation. .Iaddend..Iadd.35. The dialer chip set forth in claim 34wherein at least one of said external hardwired connections is connectedto at least one input pin of the dialer chip. .Iaddend..Iadd.36. Thedialer chip set forth in claim 35 wherein said at least one externalhardwired connection is also connected to an additional input pin of thedialer chip. .Iaddend..Iadd.37. The dialer chip set forth in claim 35further including an internal option select circuit is programmed duringa set-up mode of the dialer chip, and during said set-up mode, anaddress is generated in the dialer chip and placed on said at least oneinput pin of the dialer chip, said address also being passed throughsaid at least one external hardwired connection and received at saidadditional input pin of the dialer chip. .Iaddend..Iadd.38. A dialerwhich performs a set-up operation upon receipt of a hook switch signal..Iaddend..Iadd.39. The dialer set forth in claim 38 wherein an internaloption select circuit is programmed during said set-up operation..Iaddend..Iadd.40. The dialer chip set forth in claim 39 wherein saidinternal option select circuit selects dialing parameters of the dialersuch that, depending on the programming of said internal option selectcircuit, the dialing parameters of one of a plurality of countries canbe selected. .Iaddend..Iadd.41. The dialer chip set forth in claim 39wherein at least one external hardwired connection is connected to atleast one input pin of the dialer chip. .Iaddend..Iadd.42. The dialerchip set forth in claim 41 wherein said at least one external hardwiredconnection is connected to one input pin of the dialer chip. .Iaddend.